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PostPosted: Mon Oct 01, 2012 4:06 pm 
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Joined: Thu Aug 09, 2012 6:16 pm
Posts: 43
I just ran across this tool:
http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx shows with 25 MHz clock and output from 10.6-10.8 Mhz looking like far from a sine wave- perhaps what I see is correct for the output? Tek 453, .1uS timebase, 200mV/div, 0v ref center of display. The higher it goes, the less it looks like a sine wave. So what *should* I see going to the filter input for the DDS?

Cheers,

Bill


Attachments:
File comment: At 533KHz looks like a more like sine wave.
ad9833-25MHz-clock-.533MHzoutput.png
ad9833-25MHz-clock-.533MHzoutput.png [ 196.23 KiB | Viewed 9831 times ]
File comment: Simulated output from AD site 10.6MHz
ad9833-25MHz-clock-10.6MHzoutput.png
ad9833-25MHz-clock-10.6MHzoutput.png [ 222.43 KiB | Viewed 9831 times ]
File comment: 1uS timebase, 200mV/div, 0v ref center of display.
AD9833-waveform-IMG_5406.jpg
AD9833-waveform-IMG_5406.jpg [ 179.11 KiB | Viewed 9831 times ]
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PostPosted: Mon Oct 01, 2012 8:53 pm 
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Joined: Mon Jul 23, 2012 6:25 am
Posts: 1143
OK I'll admit that running a DDS output at ~10.7 MHz from a 25 MHz clock does sort of push it into the sinX/X range but it should look like a nice sine wave after the filter at C90, it should also be about 4X larger at C102 after being amplifier by Q5. I seem to remember that the SA612 mixer wanted about .4V peak-to-peak.


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PostPosted: Tue Oct 02, 2012 3:07 pm 
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Joined: Thu Aug 09, 2012 6:16 pm
Posts: 43
I do have a nice sine wave ~100mV P-P on the base of Q5- have not tried to transmit yet as I cannot yet change frequency. I don't know why it did not occur to me to look at the output after the filter. I guess I was convinced it was not right...

I see that the data sheet recommends: VDD - "A 0.1 µF and a 10 µF decoupling capacitor should be connected between VDD and AGND" and on CAP/2.5V "The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND."

On the schematic it shows a 10uF on CAP/2.5V Pin3, and a 100nF for decoupling on Pin2 VDD. So perhaps these are reversed- may not stop it from working but it seems worth noting.

The datasheet says "The DAC is configured for single-ended operation. An external load resistor is not required because the device has a 200 Ω resistor on board. The DAC generates an output voltage of typically 0.6 V p-p." so when I remove C69 (no load) I have ~100mV out-- it would be nice to know if that is out of spec before I needlessly remove and replace the device. Does the output drop to 100mV at the upper end of the range? That seems a bit down from the typical 600mV- but the definition of "typical" is open to interpretation.

Thanks and 73
Bill


Attachments:
File comment: DSP 610 AD9833 CAP/2.5V and decoupling
c98-c96-ad9833.png
c98-c96-ad9833.png [ 47.15 KiB | Viewed 9817 times ]
File comment: AD9833 data sheet excerpt
decoupling-cap2v5.png
decoupling-cap2v5.png [ 112.47 KiB | Viewed 9817 times ]
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PostPosted: Tue Oct 02, 2012 9:59 pm 
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Joined: Mon Jul 23, 2012 6:25 am
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Sounds about right, that should put about 0.4 V at the collector of Q5 which is just right. It's not roll-off it's SINx/x which is 0 at Fs/2 and 10.715 MHz is already moving down the curve! THe maximum for the part should be 10 MHz.


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PostPosted: Wed Oct 03, 2012 10:49 am 
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Joined: Thu Aug 09, 2012 6:16 pm
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OK Jim- makes sense now. Thanks for the help!


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